1. Field of the Invention
This invention relates generally to data processing systems and more particularly to a clocking system which is stalled to allow reliable access of firmware error routines without a time penalty to non-error cases.
2. Description of the Prior Art
In data processing systems, the speed of operation is normally controlled by a clock system. A typical clock system generates a square wave with a time period to match the speed of the logical elements of the data processing system, and in the same system to match the speed of the information being transferred between peripheral subsystems and a central processor unit (CPU) of the data processing system.
U.S. Pat. No. 4,105,978 entitled "Stretch and Stall Clock" describes a system clock mechanism which can be stretched; that is, generate pulses at more than one rate to match the speed of the CPU to the data rate of the peripheral subsystem. The system clock mechanism may be stalled and restarted immediately upon request to satisfy the requirements of some asynchronous operations.
U.S. Pat. No. 4,134,073 entitled "Clock System Having Adaptive Synchronous Feature" describes apparatus to stall the system clock in the CPU during the transfer of information between the CPU and main memory.
U.S. Pat. No. 4,241,418 entitled "Clock System Having a Dynamically Selectable Clock Period" describes apparatus for generating one of four possible predetermined clock cycle periods. The apparatus also starts up the clock cycle in a minimum period of time after the removal of a stall high signal or a stall low signal.
As performance of data processing systems is improved by the use of faster logic circuits, the clock cycle periods used in the CPU become shorter requiring components with closer tolerance. An example of the clock system providing for the adjustment of the clock frequency is described in U.S. Pat. No. 3,775,696 entitled "Synchronous Digital System Having a Multi-Speed Logic Clock Oscillator".
U.S. application Ser. No. 224,727 entitled "Adjustable Clock System Having a Dynamically Selectable Clock Period" describes apparatus for permitting the CPU clock system to generate a train of clock pulses with each clock cycle period being of a predetermined cycle time but independent of the cycle time of the preceding or succeeding clock cycle, thereby tailoring each clock cycle period to a particular microprogram step thereby maximizing the throughput of the CPU. Also a number of stall functions are described including those which are asynchronous with the firmware operation and those which are controlled by the firmware.
It should be understood that the references cited herein are those of which the applicants are aware and are presented to acquaint the reader with the level of skill in the art and may not be the closest reference to the invention. No representation is made that any search has been conducted by the applicants.